This invention relates to an MNOS type non-volatile memory device, i.e. a non-volatile semiconductor memory device having as its gate structure a metal layer--silicon nitride layer--silicon oxide layer--silicon structure, and a method of manufacturing the same.
An MNOS type non-volatile memory has a gate electrode on a gate insulating layer, and source and drain regions at either side of a channel region underneath the gate insulating layer, just as in a conventional MOS field effect transistor (which will be hereinafter referred to as an FET). However, an MNOS type non-volatile memory is different from an ordinary FET in that the gate insulating layer consists of an extremely thin layer of silicon oxide with a silicon nitride layer formed thereon. The silicon oxide layer permits charged carriers to pass therethrough due to the tunnel effect. The silicon nitride layer has a high density of trap states, and thereby captures and holds the cahrged carriers which have passed through the silicon oxide layer.
When a negative pulse is applied to the gate electrode while an n-type silicon substrate is grounded, for example, in a p-channel MNOS type non-volatile memory, positive holes as charged carriers pass through the extremely thin layer of silicon oxide into the silicon nitride layer due to the tunnel effect and are captured by the trap states therein. The relaxation time for the trap states in the silicon nitride layer under thermal equilibrium at the neighborhood of room temperature is very long. Accordingly, unless the thermal equilibrium is forcibly disturbed from the outside, the positive holes are held in the trap states. When the gate electrode is grounded with a negative pulse applied to the n-type silicon substrate and with positive holes held in the trap states, the positive holes captured by the trap states in the silicon nitride layer are excited and discharged. These positive holes pass through the extremely thin oxide layer due to the tunnel effect and are discharged into the n-type silicon substrate. The condition in which the positive holes are held in the silicon nitride layer, and the condition in which the positive holes are discharged from the silicon nitride layer, are externally displayed in the form of different FET threshold voltages. Therefore, when a voltage, the level of which is halfway between that of the threshold voltage at which the positive holes are held and that of the threshold voltage at which the positive holes are discharged, is applied to the gate electrode with the source grounded and with a negative voltage applied to the drain, an electric current does not flow between the source and drain when the positive holes are held, and an electric current flows therebetween when the positive holes have been discharged. Namely, the principle of an MNOS typ non-volatile memory resides in that it permits data to be electrically written therein, and data in the memory can either be electrically erased or stored therein indefinitely.
However, in a conventional MNOS type non-volatile memory, the density of the trap states in its silicon nitride layer is distributed uniformly through the thickness thereof. Accordingly, it is considered that the center of the density distribution of captured charged carriers is positioned within the silicon nitride layer rather than at the interface between the silicon oxide layer and the silicon nitride layer. In a memory having such a density distribution of charged carriers it is necessary to increase the voltage level or the width of the erasure pulse applied between the gate electrode and the substrate as compared with a memory in which the center of the density distribution of charged carriers is at the interface between the silicon oxide and silicon nitride layers. Namely, a memory having the center of the density distribution of charged carriers positioned in an inner region of the silicon nitride layer is inferior in erasing efficiency to a memory having the center of density distribution of the charged carriers positioned in the vicinity of the interface between the silicon nitride layer and the silicon oxide layer.
On the other hand, when charged carriers are held in a silicon nitride layer, an electric field induced by the carriers is generated therein unless the density distribution of the carriers is uniform. Consequently, the charged carriers flow to the gate electrode in the form of a Poole-Frenkel current due to the electric field referred to above, so that in practice the carrier-holding condition does not continue for a long period of time. The Poole-Frenkel current is generated due to the hopping conduction of charged carriers between the trap states in the silicon nitride layer. Therefore, the memory holding characteristics of an MNOS type non-volatile memory are improved in inverse proportion to the density of the trap states in the silicon nitride layer thereof. However, the lower the density of trap states in the silicon nitride layer, the deeper the center of the density distribution of the above captured charged carriers is in the silicon nitride layer. Accordingly, when the density of trap states in the silicon nitride film is decreased for increasing the holding time, the erasing efficiency is reduced.
In order to obtain excellent memory holding characteristics without causing a decrease in the erasing efficiency, a so-called MN.sub.1 N.sub.2 OS FET has been proposed, which employs a double silicon nitride layer consisting of a first silicon nitride layer formed on the silicon oxide layer side and having a high density of trap states, and a second silicon nitride layer formed between the first silicon nitride layer and the gate electrode and having a low density of trap states.
However, this MN.sub.1 N.sub.2 OS type of FET has a discontinuity in its dielectric constant at the interface between the first and second silicon nitride layers, so that an electric field concentration occurs at this interface. Therefore, dielectric breakdown would occur in the silicon nitride layer when a pulse voltage which is high enough to cause the carrier to be injected in or to be discharged from the silicon nitride layer, for example a pulse voltage of 30 to 35 V, is applied to the layer. Accordingly, it is necessary to make the two silicon nitride layers the same thickness. However, when the silicon nitride layers are made the same thickness, the erasing efficiency and memory holding characteristics are not improved as much as expected.